1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device equipped with redundant memory cells on the chip of the memory device.
The storage capacity per chip of semiconductor memory devices is increasing due to advances in the fine production techniques. On the other hand, it becomes more difficult to avoid faults caused in the production process. Hence, redundant memory cells are mounted on the chip in order to save faulty chips and improve the yield. Such redundant memory cells are used instead of faulty memory cells.
2. Description of the Prior Art and Related Art
FIG. 1 is a block diagram of a semiconductor memory device having a fault saving circuit. Generally, recent semiconductor memory devices such as shown in FIG. 1 are configured so that long wiring lines are segmented into parts to reduce a delay of time caused by the lines or a plurality of blocks obtained by dividing the memory cell array to perform parallel processing on a plurality of bits of data. The device shown in FIG. 1 is an example of devices having 16 memory cell blocks.
More particularly, the semiconductor memory device shown in FIG. 1 includes a memory cell array 10 having 16 divided blocks 10a, and an input/output buffer 12. The memory cell array 10 includes memory cells MC arranged in rows and columns, and redundant memory cells MCr arranged in rows and columns and intended to save faulty memory cells. Single circles denote normal memory cells MC, and double circles denote redundant memory cells MCr.
More specifically, each of the blocks 10a has redundant memory cells MCr. The memory cells MC are connected to word lines WL0, WL1, WL2, . . . and bit lines BL0, BL1, BL2, . . . . The redundant memory cells MCr are connected to redundant word lines RWL0 and RWL1 and redundant bit lines RBL0 and RBL1. A row decoder 20 includes decoder parts (including word line drivers) respectively given to the word lines, and selects one of the word lines by decoding an external row address signal. A column decoder 14 includes decoder parts respectively given to the bit lines, and selects one of the bit lines by decoding an external column address signal via I/O gates (including sense amplifier) 16 respectively given to the bit lines. Similarly, there are provided a row redundancy circuit 22 having decoder parts respectively given to the redundant word lines, a column redundancy circuit 18 having decoder parts respectively given to the redundant bit lines, and I/O gates 19 respectively given to the decoder parts of the circuit 18.
If a test performed after the production identifies a faulty memory cell indicated by the hatched circle, the column redundancy circuit 18 is programmed so that the circuit 18 selects, for example, the redundant bit line RBL0 when receiving the column address signal specifying the bit line BL1, or the row redundancy circuit 22 is programmed so that the circuit 22 selects, for example, the redundant word line RWL0 when receiving the row address signal specifying the word line WL3. Hence, the redundant memory cell MCr indicated by symbol *1 or *2 is selected instead of the faulty memory cell when the latter cell is selected.
Semiconductor memory devices having redundant structures as described above are disclosed in, for example, Japanese Laid-Open Patent Application No. 4-254998 and Japanese Laid-Open Patent Application No. 5-151798.
However, the known structure shown in FIG. 1 has the following disadvantages.
As has been described previously, the redundant memory cells MCr are arranged in each of the blocks 10a, and designed to save redundant memory cells in the corresponding blocks. Hence, the redundant memory cells MCr arranged in a block cannot save faulty memory cells arranged in another block. If a large number of faults occur in a certain block, these faulty cells cannot be saved by the redundant memory cells in the other blocks. As a result, the chip having such faults will be discarded irrespective of whether there are many available redundant cells in the other blocks. The above shows that the efficiency of saving faulty cells by the fault saving circuit (the redundant circuit part) shown in FIG. 1 is low.
In order to improve the saving efficiency, it is necessary to provide a larger number of redundant memory cells MCr in each of the blocks 10a. However, this method needs a larger area on the chip to be occupied by the fault saving circuit.
It will be noted that the above disadvantages becomes more serious as the number of blocks increases. Nowadays, there is a trend to increase the storage capacity and thus increase the number of memory cell blocks. Under the above circumstance, the above disadvantages should be solved.
In order to overcome the above disadvantages, the inventors initially considered that the redundant memory cells are disposed separately from the blocks. That is, an array of redundant memory cells only is provided outside of the blocks of memory cells.
FIG. 2 is a block diagram of a semiconductor memory device taking into consideration the above arrangement. The semiconductor memory device shown in FIG. 2 includes a memory cell array 24 having a plurality of blocks 24a having no redundant memory cells, an input/output buffer/redundant data switching circuit 26, a row redundancy array 28 and a column redundancy array 30. Each of the blocks 24a includes the circuit shown in FIG. 1 except for the fault saving circuit. As shown in FIG. 2, the row redundancy array 28 has bit lines BL0 and BL1 equal in number to the bit lines in one block, redundant word lines RWL0, RWL1, . . . , a column decoder 32, and an I/O gate 34. The row redundancy array 28 further includes a row redundancy circuit 36, which includes unit circuits respectively given to the redundant word lines. Each of the unit circuits stores the row and block addresses of a faulty word line.
The external address applied to the memory cell array 24 shown in FIG. 2 includes the external row address and the external column address. In the memory device, the address is separated from a block address for selecting one of the blocks 24a, an address for selecting one of the word lines, and an address for selecting one of the bit lines. Hereinafter, the address for selecting one word line, and the address for selecting one bit line are referred to as a row address and a column address, respectively. The above-described row redundancy circuit 36 stores the block address of a faulty word line, and is hence capable of identifying the block having such a faulty word line. That is, one row redundancy array 28 can be given in common to the plural blocks 24a.
The row redundancy circuit 36 drives, when the input address coincides with the stored address (the row address and the block address), the corresponding redundant word line. After the redundant word line is driven and settled, the redundant memory cell MCr is selected in accordance with the column address, and data in the selected redundant memory cell MCr is sent to the I/O buffer/redundant data switching circuit 26.
As shown in FIG. 2, the column redundancy circuit 30 includes word lines WL0, WL1, . . . equal in number of those of one block of the array 24, redundant bit lines RBL0, RBL1, . . . , a column redundancy circuit 38, and an I/O gate 40. The column redundancy circuit 38 includes unit circuits respectively given to the redundant bit lines. Each of the unit circuits stores the column and block addresses of a faulty bit line.
After the word line is driven and settled in accordance with the applied row address, the applied column and block addresses are compared with the column and block addresses stored in the column redundancy circuit 38. When the applied addresses coincide with the stored address, the corresponding redundant bit line is selected, and data in the selected redundant memory cell MCr is sent to the I/O buffer/redundant data switching circuit 26. When the applied addresses do not coincide with the stored addresses, the column redundancy circuit 30 drives the word line uselessly.
However, the structure shown in FIG. 2 has a disadvantage in that if the row redundancy array 28 has a bit-line fault, it cannot save a faulty word line. For example, if the bit line BL0 in the row redundancy array 28 is broken (open) in a position indicated by symbol X shown in FIG. 2, the memory cell connected to the faulty word line and the bit line BL0 is no longer saved even when the faulty word line is replaced by the redundant word line. Similarly, the column redundancy array 30 has a word-line fault, it cannot save a faulty bit line. For example, if the word line WL1 in the column redundancy array 30 is broken (open) in a position indicated by symbol X, the memory cell connected to the word line WL1 and the faulty bit line is no longer saved even when the faulty bit line is replaced by the redundant bit line.